Semiconductor memory apparatus and semiconductor memory system for controlling transmission bandwidth

ABSTRACT

A semiconductor memory apparatus includes a memory bank circuit and a bandwidth control circuit. The memory bank circuit stores normal data, an error correction code, and a meta information code. The bandwidth control circuit controls bandwidths of the error correction code and the meta information code based on bandwidth option information.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean application number 10-2021-0098687, filed on Jul. 27, 2021, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments may generally relate to a semiconductor memoryapparatus and a semiconductor memory system, and more particularly, to asemiconductor memory apparatus and a semiconductor memory system whichprovide an error correction code and a meta information code.

2. Related Art

In general, integrated circuits including semiconductor apparatuses andsemiconductor memory apparatuses transmit and receive lots of data.Errors in the transmitted and received data occur due to variousreasons. Since the errors occurring in the data cause fatal errors inoperations of the integrated circuits, solutions for the errors arerequired. Error correction code (ECC) engines are typically used toresolve the errors occurring in the data.

ECC engines detect errors occurring in data and correct the errors togenerate stable data. The ECC engines largely perform two operations.The first operation is an operation which decodes data to generate errorcorrection parity bit information which can correct errors in the data.The second operation is an operation which encodes the error correctionparity bit information and the data to generate normal data. With thedevelopment in the process technology of the integrated circuits, atleast partial functions of the ECC engine are mounted on the latestintegrated circuits to enhance operation efficiency. This is called anon-chip ECC scheme.

The integrated circuits use meta information codes to perform circuitoperations more efficiently. The meta information codes includeadditional information in transmitting and receiving data, for example,various information such as temperature information, status information,and operation information. The meta information codes also includeinformation related to a read operation and a write operation of dataand error information of data in the read operation and the writeoperation. For example, the error information of the data includeinformation for attempt to correct errors in the corresponding data inthe read operation, status information of an error, information for thenumber of errors, information for an address of an error, informationfor frequency of an error, and the like. Further, the meta informationcodes also include various information for a control circuit whichtransmits and receives data to and from the integrated circuit.Specifically, the meta information code include reliability informationfor data.

With the developments in the process and circuit technology of theintegrated circuits, the amount of data transmitted to and received fromthe integrated circuits has been increasing. As the amount of data isincreased, the amount of error correction codes corresponding to theerror correction parity bit information has also been increasinglyincreased. Further, the amount of meta information codes has also beenincreasingly increased. Therefore, the integrated circuits are in adesperate need of efficient management of error correction codes andmeta information codes.

SUMMARY

In an embodiment of the present disclosure, a semiconductor memoryapparatus may include: a memory bank circuit configured to store normaldata, an error correction code, and a meta information code; and abandwidth control circuit configured to set a ratio between a memoryregion of the memory bank circuit in which the error correction code isto be stored and a memory region of the memory bank circuit in which themeta information code is to be stored by controlling transmissionbandwidths of the error correction code and the meta information codebased on bandwidth option information.

In an embodiment of the present disclosure, a semiconductor memoryapparatus may include: a memory bank circuit configured to store normaldata and a meta information code; an error code generation circuitconfigured to generate an error correction code by decoding the normaldata; and a bandwidth control circuit configured to set outputbandwidths of the error correction code and the meta information code bycontrolling transmission bandwidths of the error correction code and themeta information code based on bandwidth option information.

In an embodiment of the present disclosure, a semiconductor memorysystem may include: a controller configured to transmit normal data, anerror correction code, and a meta information code and configured toprovide bandwidth option information; and a semiconductor memoryapparatus configured to receive and store the normal data, the errorcorrection code, and the meta information code, from the controller, andtransmit the normal data, the error correction code, and the metainformation code that are stored therein to the controller based on thecontroller. Transmission bandwidths of the error correction code and themeta information code that are transmitted and received between thecontroller and the semiconductor memory apparatus may be controlledbased on the bandwidth option information.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the subjectmatter of the present disclosure will be more clearly understood fromthe following detailed description taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a block diagram illustrating a configuration of asemiconductor memory apparatus according to an embodiment of the presentdisclosure;

FIG. 2 is a block diagram illustrating a configuration of a memory bankcircuit of FIG. 1 ;

FIG. 3 is a block diagram illustrating a configuration of asemiconductor memory apparatus according to an embodiment of the presentdisclosure;

FIG. 4 is a block diagram illustrating a configuration of asemiconductor memory apparatus according to an embodiment of the presentdisclosure;

FIG. 5 is a block diagram illustrating a configuration of asemiconductor memory apparatus according to an embodiment of the presentdisclosure; and

FIG. 6 is a block diagram illustrating a configuration of asemiconductor memory system according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

The description of the present disclosure is an embodiment for astructural and/or functional description. The scope of rights of thepresent disclosure should not be construed as being limited toembodiments described in the specification. That is, the scope of rightsof the present disclosure should be understood as including equivalents,which may realize the technical spirit, because an embodiment may bemodified in various ways and may have various forms. Furthermore,objects or effects proposed in the present disclosure do not mean that aspecific embodiment should include all objects or effects or includeonly such effects. Accordingly, the scope of rights of the presentdisclosure should not be understood as being limited thereby.

The meaning of the terms that are described in this application shouldbe understood as follows.

The terms, such as the “first” and the “second,” are used to distinguishone element from another element, and the scope of the presentdisclosure should not be limited by the terms. For example, a firstelement may be named a second element. Likewise, the second element maybe named the first element.

An expression of the singular number should be understood as includingplural expressions, unless clearly expressed otherwise in the context.The terms, such as “include” or “have,” should be understood asindicating the existence of a set characteristic, number, step,operation, element, part, or a combination thereof, not excluding apossibility of the existence or addition of one or more othercharacteristics, numbers, steps, operations, elements, parts, or acombination thereof.

In each of the steps, symbols (e.g., a, b, and c) are used forconvenience of description, and the symbols do not describe an order ofthe steps. The steps may be performed in an order different from theorder described in the context unless a specific order is clearlydescribed in the context. That is, the steps may be performed accordingto a described order, may be performed substantially at the same time asthe described order, or may be performed in reverse order of thedescribed order.

All the terms used herein, including technological or scientific terms,have the same meanings as those that are typically understood by thoseskilled in the art, unless otherwise defined. Terms defined in commonlyused dictionaries should be construed as with the same meanings as thosein the context in related technology and should not be construed as withideal or excessively formal meanings, unless clearly defined in theapplication.

Embodiments are provided to a semiconductor memory apparatus and asemiconductor memory system capable of controlling transmissionbandwidths of an error correction code and a meta information code.

FIG. 1 is a block diagram illustrating a configuration of asemiconductor memory apparatus 100 according to an embodiment.

Referring to FIG. 1 , the semiconductor memory apparatus 100 may includea memory bank circuit 110 and a bandwidth control circuit 120.

The memory bank circuit 110 may be configured to store normal dataDAT_NR, an error correction code COD_EC, and a meta information codeCOD_MT. Here, the normal data DAT_NR may include data that is used in aread operation and a write operation of the semiconductor memoryapparatus 100. The error correction code COD_EC may include errorcorrection parity bit information for the normal data DAT_NR. The metainformation code COD_MT may include reliability information for thenormal data DAT_NR.

The memory bank circuit 110 may be configured of a memory cell circuit,a latch circuit, a register circuit, and the like. Here, for clarity, ithas been illustrated in the embodiment that the normal data DAT_NR, theerror correction code COD_EC, and the meta information code COD_MT maybe stored in the memory bank circuit 110 that is configured of thememory cell circuits.

The memory bank circuit 110 will be described in detail below. Thememory bank circuit 110 may include first to third memory regions 110-1,110-2, and 110-3. The first memory region 110-1 may be configured tostore the normal data DAT_NR. The second memory region 110-2 may beconfigured to store the error correction code COD_EC. The third memoryregion 110-3 may be configured to store the meta information codeCOD_MT.

Transmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT may be controlled based on bandwidth optioninformation INF_OP, and detailed description thereof will be made below.For example, a ratio between the second memory region 110-2 in which theerror correction code COD_EC is to be stored and the third memory region110-3 in which the meta information code COD_MT is to be stored may bevaried. In this example, the ratio between memory regions in the secondmemory region 110-2 and the third memory region 110-3 may be varied asindicated by an arrow that is illustrated between the second memoryregion 110-2 and the third memory region 110-3.

For example, the memory bank circuit 110 may be set in such a mannerthat at least a portion of the third memory region 110-3 may become apart of the second memory region 110-2 based on the bandwidth optioninformation INF_OP. In another example, the memory bank circuit 110 maybe set in such a manner that at least a portion of the second memoryregion 110-2 may become a part of the third memory region 110-3 based onthe bandwidth option information INF_OP.

The bandwidth control circuit 120 may be configured to control thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT based on the bandwidth option informationINF_OP. The bandwidth control circuit 120 may be configured to set theratio between the memory regions, in which the error correction codeCOD_EC and the meta information code COD_MT are to be stored, bycontrolling the transmission bandwidths of the error correction codeCOD_EC and the meta information code COD_MT based on the bandwidthoption information INF_OP. Here, the bandwidth option information INF_OPmay be provided, for example, from a mode register set. The bandwidthoption information INF_OP may include transmission bandwidth informationfor at least one code of the error correction code COD_EC and the metainformation code COD_MT. Although not shown in FIG. 1 , the bandwidthcontrol circuit 120 may include configurations for controlling a readoperation and a write operation of the memory bank circuit 110 with theabove-described configuration.

Hereinafter, the transmission bandwidths of the error correction codeCOD_EC and the meta information code COD_MT that are output from thebandwidth control circuit 120 will be described. For clarity, it hasbeen defined in the embodiment that the transmission bandwidthcorresponding to the error correction code COD_EC is ‘e’ and thetransmission bandwidth corresponding to the meta information code COD_MTis ‘m’. It has been defined in the embodiment that a sum of thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT output from the bandwidth control circuit 120 is‘n’ (where n is a natural number). Accordingly, a total transmissionbandwidth of the error correction code COD_EC of the transmissionbandwidth e and the meta information code COD_MT of the transmissionbandwidth m may be ‘n’. It has been assumed in the embodiment that n is48.

When the bandwidth option information INF_OP includes information forsetting the transmission bandwidth of the error correction code COD_ECas 48, the bandwidth control circuit 120 may output the error correctioncode COD_EC with the transmission bandwidth of 48. For example, thetransmission bandwidth e of the error correction code COD_EC may be 48,which is the total transmission bandwidth n, and the transmissionbandwidth m of the meta information code COD_MT may be 0 (zero). In thisexample, the error correction code COD_EC may be stored in both of thesecond memory region 110-2 and the third memory region 110-3.Specifically, the second memory region 110-2 may be extended to thethird memory region 110-3, and thus, the entire memory region of thethird memory region 110-3 may become a part of the second memory region110-2.

When the bandwidth option information INF_OP includes information forsetting the transmission bandwidth of the meta information code COD_MTas 48, the bandwidth control circuit 120 may output the meta informationcode COD_MT with the transmission bandwidth of 48. For example, thetransmission bandwidth m of the meta information code COD_MT may be 48,which is the total transmission bandwidth n, and the transmissionbandwidth e of the error correction code COD_EC may be 0 (zero). In thisexample, the meta information code COD_MT may be stored in both of thesecond memory region 110-2 and the third memory region 10_3.Specifically, the third memory region 110-3 may be extended to thesecond memory region 110-2, and thus, the entire memory region of thesecond memory region 110-2 may become a part of the third memory region110-3.

The relationship between the transmission bandwidths of the errorcorrection code COD_EC and the meta information code COD_MT based on thebandwidth option information INF_OP may be generalized below.

When the bandwidth option information INF_OP includes information forsetting the transmission bandwidth of the error correction code COD_ECas ‘e’, the bandwidth control circuit 120 may output the errorcorrection code COD_EC with the transmission bandwidth of ‘e’ and outputthe meta information code COD_MT with the transmission bandwidth of‘48-e’. For example, the second memory region 110-2 may include a memoryregion corresponding to the transmission bandwidth ‘e’, and the thirdmemory region 110-3 may include a memory region corresponding to thetransmission bandwidth ‘48-e’.

Through the above-described configuration and operation, the bandwidthcontrol circuit 120 may set the transmission bandwidths of the codecorrection code COD_EC and the meta information code COD_MT based on thebandwidth option information INF_OP. The ratio between the memoryregions of the second memory region 110-2 and the third memory region110-3, in which the error correction code COD_EC and the metainformation code COD_MT are to be stored, may be set according to theset transmission bandwidths of the error correction code COD_EC and themeta information code COD_MT.

Accordingly, when the total transmission bandwidth n is used as thetransmission bandwidth of the error correction code COD_EC, thesemiconductor memory apparatus 100 may store more error correctionparity bit information that is required for an error correctionoperation for the normal data DAT_NR. When the total transmissionbandwidth n is used as the transmission bandwidth of the metainformation code COD_MT, the semiconductor memory apparatus 100 maystore more reliability information for the normal data DAT_NR. Thesemiconductor memory apparatus 100 may efficiently store the errorcorrection code COD_EC and the meta information code COD_MT without anadditional configuration for memory regions of the second memory region110-2 and the third memory region 110-3, by setting the ratio betweenthe memory regions of the second memory region 110-2 and the thirdmemory region 110-3.

The semiconductor memory apparatus 100 according to an embodiment mayset the transmission bandwidths of the error correction code COD_EC andthe meta information code COD_MT based on the bandwidth optioninformation INF_OP. The semiconductor memory apparatus 100 mayefficiently store the error correction code COD_EC and the metainformation code COD_MT according to the set transmission bandwidths.

FIG. 2 is a block diagram illustrating a configuration of the memorybank circuit 110 of FIG. 1 .

Referring to FIG. 2 , the memory bank circuit 110 may include aplurality of unit memory mat circuits 210. From the memory bank circuit110, illustrated in FIG. 1 , the plurality of unit memory mat circuits210 may store the normal data DAT_NR, the error correction code COD_EC,and the meta information code COD_MT.

Hereinafter, for clarity, one unit memory mat circuit 210, among theplurality of unit memory mat circuits 210, will be described as arepresentative. The unit memory mat circuit 210 may include first tothird memory regions 210_1, 210_2, and 210_3.

The first memory region 210_1 may be configured to store the normal dataDAT_NR. The second memory region 210_2 may be configured to store theerror correction code COD_EC. The third memory region 210_3 may beconfigured to store the meta information code COD_MT. When one unitmemory mat circuit 210 is activated according to a read operation and awrite operation for the normal data DAT_NR, the one unit memory matcircuit 210 may simultaneously output the error correction code COD_ECand the meta information code COD_MT that corresponds to the normal dataDAT_NR.

The semiconductor memory apparatus 100, according to an embodiment, maystore the error correction code COD_EC and the meta information codeCOD_MT with information related to the normal data DAT_NR in one unitmemory mat circuits 210. Accordingly, the semiconductor memory apparatus100 may more quickly perform the read and write operations on the errorcorrection code COD_EC and the meta information code COD_MT related tothe normal data DAT_NR.

FIG. 3 is a block diagram illustrating a configuration of asemiconductor memory apparatus 300 according to an embodiment.

Referring to FIG. 3 , the semiconductor memory apparatus 300, accordingto an embodiment, may include a memory bank circuit 310, a bandwidthcontrol circuit 320, and an error analysis circuit 330. Here, the memorybank circuit 310 and the bandwidth control circuit 320 may correspond tothe memory bank circuit 110 and the bandwidth control circuit 120 ofFIG. 1 . Therefore, the detailed operations of the memory bank circuit310 and the bandwidth control circuit 320 of FIG. 3 will be omitted.

Hereinafter, the error analysis circuit 330 will be described in detail.

The error analysis circuit 330 may be configured to analyze and detectan error rate of the normal data DAT_NR based on the error correctioncode COD_EC. As described above, the error correction code COD_EC mayinclude the error correction parity bit information for an errorcorrection operation of the normal data DAT_NR. Accordingly, when theerror correction code COD_EC is analyzed, the error rate of the normaldata DAT_NR may be analyzed and detected. The error analysis circuit 330may generate the bandwidth option information INF_OP that corresponds tothe error rate of the normal data DAT_NR.

When the error rate of the normal data DAT_NR is large, the erroranalysis circuit 330 may control the bandwidth option information INF_OPso that much more error correction code COD_EC may be output from thebandwidth control circuit 320. For clarity, it is assumed that the totaltransmission bandwidth n is 48, and the transmission bandwidth of theerror correction code COD_EC previously output from the bandwidthcontrol circuit 320 is 32. Accordingly, the transmission bandwidth ofthe meta information code COD_MT that is previously output from thebandwidth control circuit 320 may be 16.

When the error rate of the normal data DAT_NR is large, the bandwidthcontrol circuit 320 may output the error correction code COD_EC with thetransmission bandwidth of 40 that is larger than the previoustransmission bandwidth of 32 based on the bandwidth option informationINF_OP. Accordingly, the transmission bandwidth of the error correctioncode COD_EC may be increased. The transmission bandwidth of the metainformation code COD_MT may be reduced from 16 to 8. Subsequently, whenthe error rate of the normal data DAT_NR is very large, the bandwidthcontrol circuit 320 may output the error correction code COD_EC with themaximum transmission bandwidth of 48. The meta information code COD_MTmight not be output. Accordingly, the bandwidth control circuit 320 maycontrol the transmission bandwidth of the error correction code COD_ECto be increased based on the increase for the error rate of the normaldata DAT_NR.

When the error rate of the normal data DAT_NR is small, the erroranalysis circuit 330 may control the bandwidth option information INF_OPso that much more meta information code COD_MT may be output from thebandwidth control circuit 320. For clarity, when it is assumed that thetransmission bandwidth of the meta information code COD_MT that ispreviously output from the bandwidth control circuit 320 is 16, thetransmission bandwidth of the code correction code COD_EC that ispreviously output from the bandwidth control circuit 320 may be 32.

When the error rate of the normal data DAT_NR is small, the bandwidthcontrol circuit 320 may output the meta information code COD_MT with thetransmission bandwidth of 20 that is larger than the previoustransmission bandwidth of 16 based on the bandwidth option informationINF_OP. Accordingly, the transmission bandwidth of the meta informationcode COD_MT may be increased. The transmission bandwidth of the errorcorrection code COD_EC may be reduced from 32 to 28. Subsequently, whenthe error rate of the normal data DAT_NR is very small, the bandwidthcontrol circuit 320 may output the meta information code COD_MT with themaximum transmission bandwidth of 48. The error correction code COD_ECmight not be output. Accordingly, the bandwidth control circuit 320 maycontrol the transmission bandwidth of the meta information code COD_MTto be increased based on the decrease for the error rate of the normaldata DAT_NR.

The semiconductor memory apparatus 300 according to an embodiment maycontrol the transmission bandwidth of the error correction code COD_ECand the transmission bandwidth of the meta information code COD_MT basedon the increase and decrease of the error rate of the normal dataDAT_NR.

FIG. 4 is a block diagram illustrating a configuration of asemiconductor memory apparatus 400 according to an embodiment.

Referring to FIG. 4 , the semiconductor memory apparatus 400 accordingto an embodiment may include a memory bank circuit 410, an error codegeneration circuit 420, and a bandwidth control circuit 430.

The memory bank circuit 410 may be configured to store the normal dataDAT_NR and the meta information code COD_MT. The memory bank circuit 410may correspond to the memory bank circuit 110 of FIG. 1 . For example,the error correction code COD_EC may be stored in the error codegeneration circuit 420 to be described later. In another example, theerror correction code COD_EC may be stored in the memory bank circuit410 as described in FIGS. 1 to 3 .

The error code generation circuit 420 may be configured to generate theerror correction code COD_EC by decoding the normal data DAT_NR. Theerror code generation circuit 420 may be configured to include an errorcorrection code (ECC) engine.

The bandwidth control circuit 430 may be configured to control thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT based on the bandwidth option informationINF_OP. The bandwidth control circuit 430 may be configured to set theoutput bandwidths of the error correction code COD_EC and the metainformation code COD_MT by controlling the transmission bandwidths ofthe error correction code COD_EC and the meta information code COD_MT.The bandwidth control circuit 430 may include configurations foroutputting data to an external device.

The bandwidth control circuit 430 may receive the normal data DAT_NR andoutput the normal data DAT_NR with a transmission bandwidth d (where dis a natural number). The bandwidth control circuit 430 may receive theerror correction code COD_EC and the meta information code COD_MT andmay output the error correction code COD_EC and the meta informationcode COD_MT with the transmission bandwidth n. For example, the errorcorrection code COD_EC may be output with the transmission bandwidth e,out of the transmission bandwidth n, and the meta information codeCOD_MT may be output with the transmission bandwidth m, out of thetransmission bandwidth n. The bandwidth control circuit 430 maycorrespond to the bandwidth control circuit 120 of FIG. 1 , and thus,detailed description for the bandwidth control circuit 430 will beomitted.

Hereinafter, an operation of the bandwidth control circuit 430 will besimply described.

When the bandwidth option information INF_OP includes information forsetting the transmission bandwidth of the error correction code COD_ECas 48, the bandwidth control circuit 430 may output the error correctioncode COD_EC with the output bandwidth of 48. For example, the bandwidthcontrol circuit 430 may output the error correction code COD_EC through48 transmission lines.

When the bandwidth option information INF_OP includes information forsetting the transmission bandwidth of the meta information code COD_MTas 48, the bandwidth control circuit 430 may output the meta informationcode COD_MT with the output bandwidth of 48. For example, the bandwidthcontrol circuit 430 may output the meta information code COD_MT through48 transmission lines.

Through the above-described configuration and operation, thesemiconductor memory apparatus 400 may set the output bandwidth of theerror correction code COD_EC and the output bandwidth of the metainformation code COD_MT based on the bandwidth option informationINF_OP. Accordingly, the semiconductor memory apparatus 400 may providemore error correction code COD_EC to an external device through all ntransmission lines. The semiconductor memory apparatus 400 may providemore meta information code COD_MT to an external device through all ntransmission lines.

FIG. 5 is a block diagram illustrating a configuration of asemiconductor memory apparatus 500 according to an embodiment.

Referring to FIG. 5 , the semiconductor memory apparatus 500 may includea memory bank circuit 510, an error code generation circuit 520, abandwidth control circuit 530, and an error analysis circuit 540. Here,the memory bank circuit 510, the error code generation circuit 520, andthe bandwidth control circuit 530 may correspond to the memory bankcircuit 410, the error code generation circuit 420, and the bandwidthcontrol circuit 430 of FIG. 4 . The error analysis circuit 540 maycorrespond to the error analysis circuit 330 of FIG. 3 .

Hereinafter, a circuit operation of the semiconductor memory apparatus500 will be simply described.

The error analysis circuit 540 may be configured to analyze and detectthe error rate of the normal data DAT_NR based on the error correctioncode COD_EC.

When the error rate of the normal data DAT_NR is large, the erroranalysis circuit 540 may control the bandwidth option information INF_OPso that more error correction code COD_EC may be output from thebandwidth control circuit 530. For example, the bandwidth controlcircuit 530 may control the transmission bandwidth of the errorcorrection code COD_EC to be increased based on an increase of the errorrate of the normal data DAT_NR. In this example, the bandwidth controlcircuit 530 may control the output bandwidth of the error correctioncode COD_EC to be increased based on the transmission bandwidth of theerror correction code COD_EC.

When the error rate of the normal data DAT_NR is small, the erroranalysis circuit 540 may control the bandwidth option information INF_OPso that more meta information code COD_MT may be output from thebandwidth control circuit 530. For example, the bandwidth controlcircuit 530 may control the transmission bandwidth of the metainformation code COD_MT to be increased based on a decrease of the errorrate of the normal data DAT_NR. In this example, the bandwidth controlcircuit 530 may control the output bandwidth of the meta informationcode COD_MT to be increased based on the transmission bandwidth of themeta information code COD_MT.

The semiconductor memory apparatus 500 may set the transmissionbandwidth of the error correction code COD_EC and the transmissionbandwidth of the meta information code COD_MT based on the error rate ofthe normal data DAT_NR. Further, the semiconductor memory apparatus 500may efficiently output the error correction code COD_EC and the metainformation code COD_MT with the output bandwidths that correspond tothe error rate of the normal data DAT_NR without additional transmissionlines.

FIG. 6 is a block diagram illustrating a configuration of asemiconductor memory system 600 according to an embodiment.

Referring to FIG. 6 , the semiconductor memory system 600 may include acontroller 610 and a semiconductor memory apparatus 620.

The controller 610 may be configured to transmit the normal data DAT_NR,the error correction code COD_EC, and the meta information code COD_MTto the semiconductor memory apparatus 620 and may provide the bandwidthoption information INF_OP to the semiconductor memory apparatus 620. Thecontroller 610 may provide a command signal CMD and an address signalADD to the semiconductor memory apparatus 620 and may control variousoperations of the semiconductor memory apparatus 620 in addition to aread operation and a write operation of the semiconductor memoryapparatus 620. The controller 610 may control the operations of thesemiconductor memory apparatus 620 based on the command signal CMD. Thecontroller 610 may control the normal data DAT_NR, the error correctioncode COD_EC, and the meta information code COD_MT to be stored inpositions of the semiconductor memory apparatus 620 that corresponds tothe address signal ADD.

Next, the semiconductor memory apparatus 620 may be configured toreceive and store the normal data DAT_NR, the error correction codeCOD_EC, and the meta information code COD_MT from the controller 610.The semiconductor memory apparatus 620 may be configured to transmit thenormal data DAT_NR, the error correction code COD_EC, and the metainformation code COD_MT to the controller 610 based on the controller610.

For example, the controller 610 may include the bandwidth controlcircuit 430 of FIG. 4 . Although not shown in FIG. 6 , the bandwidthcontrol circuit that is included in the controller 610 may control thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT based on the bandwidth option informationINF_OP. For example, the controller 610 may set the output bandwidths ofthe error correction code COD_EC and the meta information code COD_MT bycontrolling the transmission bandwidths of the error correction codeCOD_EC and the meta information code COD_MT. In this example, thecontroller 610 may output the error correction code COD_EC with thetransmission bandwidth e and output the meta information code COD_MTwith the transmission bandwidth m based on the bandwidth optioninformation INF_OP.

In another example, the semiconductor memory apparatus 620 may includethe bandwidth control circuit 430 of FIG. 4 like the controller 610.Although not shown in FIG. 6 , the bandwidth control circuit that isincluded in the semiconductor memory apparatus 620 may control thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT based on the bandwidth option informationINF_OP. For example, the semiconductor memory apparatus 620 may set theoutput bandwidths of the error correction code COD_EC and the metainformation code COD_MT by controlling the transmission bandwidths ofthe error correction code COD_EC and the meta information code COD_MT.In this example, the semiconductor memory device 620 may output theerror correction code COD_EC with the transmission bandwidth e andoutput the meta information code COD_MT with the transmission bandwidthm based on the bandwidth option information INF_OP.

The semiconductor memory system 600 may control the transmissionbandwidths of the error correction code COD_EC and the meta informationcode COD_MT that are transmitted and received between the controller 610and the semiconductor memory apparatus 620 based on the bandwidth optioninformation INF_OP.

In another example, the semiconductor memory apparatus 620 may includethe bandwidth control circuit 120 of FIG. 1 . Although not shown in FIG.6 , the bandwidth control circuit that is included in the semiconductormemory apparatus 620 may control the transmission bandwidths of theerror correction code COD_EC and the meta information code COD_MT basedon the bandwidth option information INF_OP. For example, thesemiconductor memory apparatus 620 may set the ratio between the memoryregions, in which the error correction code COD_EC and the metainformation code COD_MT are to be stored, by controlling thetransmission bandwidths of the error correction code COD_EC and the metainformation code COD_MT. In this example, the semiconductor memorydevice 620 may control the ratio between the memory regions, in whichthe error correction code COD_EC and the meta information code COD_MTare to be stored based on the bandwidth option information INF_OP.

The semiconductor memory system 600 may control the ratio between thememory regions, in which the error correction code COD_EC and the metainformation code COD_MT are to be stored, based on the bandwidth optioninformation INF_OP.

The above described embodiments of the present invention are intended toillustrate and not to limit the present invention. Various alternativesand equivalents are possible. The invention is not limited by theembodiments described herein. Nor is the invention limited to anyspecific type of semiconductor device. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor memory apparatus comprising: amemory bank circuit configured to store normal data, an error correctioncode, and a meta information code; and a bandwidth control circuitconfigured to set a ratio between a memory region of the memory bankcircuit in which the error correction code is to be stored and a memoryregion of the memory bank circuit in which the meta information code isto be stored by controlling transmission bandwidths of the errorcorrection code and the meta information code based on bandwidth optioninformation.
 2. The semiconductor memory apparatus of claim 1, whereinthe error correction code includes error correction parity bitinformation for the normal data, and the meta information code includesreliability information for the normal data.
 3. The semiconductor memoryapparatus of claim 1, wherein the memory bank circuit includes: a firstmemory region configured to store the normal data; a second memoryregion configured to store the error correction code; and a third memoryregion configured to store the meta information code, wherein the memorybank circuit is configured to set, based on the bandwidth optioninformation, so that at least a portion of the third memory regionbecomes a part of the second memory region or at least a portion of thesecond memory region becomes a part of the third memory region.
 4. Thesemiconductor memory apparatus of claim 3, wherein the first to thirdmemory regions are included in one unit memory mat circuit.
 5. Thesemiconductor memory apparatus of claim 1, wherein the bandwidth optioninformation includes transmission bandwidth information for at least onecode of the error correction code and the meta information code.
 6. Thesemiconductor memory apparatus of claim 1, further comprising an erroranalysis circuit configured to analyze and detect an error rate of thenormal data based on the error correction code and generate thebandwidth option information based on the error rate of the normal data.7. The semiconductor memory apparatus of claim 1, wherein the bandwidthcontrol circuit is configured to control the transmission bandwidth ofthe error correction code based on an increase of an error rate of thenormal data and control the transmission bandwidth of the metainformation code based on a decrease of the error rate of the normaldata.
 8. A semiconductor memory apparatus comprising: a memory bankcircuit configured to store normal data and a meta information code; anerror code generation circuit configured to generate an error correctioncode by decoding the normal data; and a bandwidth control circuitconfigured to set output bandwidths of the error correction code and themeta information code by controlling transmission bandwidths of theerror correction code and the meta information code based on bandwidthoption information.
 9. The semiconductor memory apparatus of claim 8,wherein the error correction code includes error correction parity bitinformation for the normal data, and the meta information code includesreliability information for the normal data.
 10. The semiconductormemory apparatus of claim 8, wherein the memory bank circuit isconfigured to store the error correction code that is provided from theerror code generation circuit and configured to provide the stored errorcorrection code to the bandwidth control circuit.
 11. The semiconductormemory apparatus of claim 8, wherein the memory bank circuit includes aplurality of unit memory mat circuits, and each of the plurality of unitmemory mat circuits includes: a first memory region configured to storethe normal data; a second memory region configured to store the errorcorrection code; and a third memory region configured to store the metainformation code, wherein the unit memory mat circuit is set, based onthe bandwidth option information, so that at least a portion of thethird memory region becomes a part of the second memory region, or atleast a portion of the second memory region becomes a part of the thirdmemory region.
 12. The semiconductor memory apparatus of claim 8,wherein the bandwidth option information includes transmission bandwidthinformation for at least one code of the error correction code and themeta information code.
 13. The semiconductor memory apparatus of claim8, further comprising an error analysis circuit configured to analyzeand detect an error rate for the normal data based on the errorcorrection code and generate the bandwidth option information based onthe error rate for the normal data.
 14. The semiconductor memoryapparatus of claim 8, wherein the bandwidth control circuit isconfigured to control the output bandwidth of the error correction codebased on an increase of an error rate of the normal data and control theoutput bandwidth of the meta information code based on a decrease of theerror rate of the normal data.
 15. A semiconductor memory systemcomprising: a controller configured to transmit normal data, an errorcorrection code, and a meta information code and configured to providebandwidth option information; and a semiconductor memory apparatusconfigured to receive and store the normal data, the error correctioncode, and the meta information code from the controller, and transmitthe normal data, the error correction code, and the meta informationcode that are stored therein to the controller based on the controller,wherein transmission bandwidths of the error correction code and themeta information code that are transmitted and received between thecontroller and the semiconductor memory apparatus are controlled basedon the bandwidth option information.
 16. The semiconductor memory systemof claim 15, wherein the controller includes a bandwidth control circuitconfigured to set output bandwidths of the error correction code and themeta information code by controlling the transmission bandwidths of theerror correction code and the meta information code based on bandwidthoption information.
 17. The semiconductor memory system of claim 15,wherein the semiconductor memory apparatus includes a bandwidth controlcircuit configured to set output bandwidths of the error correction codeand the meta information code by controlling the transmission bandwidthsof the error correction code and the meta information code based onbandwidth option information.
 18. The semiconductor memory system ofclaim 15, wherein the semiconductor memory apparatus includes abandwidth control circuit configured to set a ratio between a memoryregion in which the error correction code is to be stored and a memoryregion in which the meta information code is to be stored by controllingtransmission bandwidths of the error correction code and the metainformation code based on bandwidth option information.
 19. Thesemiconductor memory system of claim 15, wherein the error correctioncode includes error correction parity bit information for the normaldata, and the meta information code includes reliability information forthe normal data.
 20. The semiconductor memory system of claim 15,wherein the bandwidth option information includes transmission bandwidthinformation for at least one code of the error correction code and themeta information code.